1. Field of the Invention
This patent document relates generally to communication apparatus including radio frequency (RF) circuits and, more particularly, to bus arbitration of bus masters within digital processing circuits of communication apparatus that implement time domain isolation techniques.
2. Description of the Related Art
High performance wireless communication apparatus such as RF receivers, transmitters, and transceivers typically include RF front-end circuitry that operates on an RF signal being received or transmitted. For example, the front-end circuitry may down-convert a received RF signal to baseband and/or up-convert a baseband signal for RF transmission.
The RF front-end circuitry typically includes analog circuits such as low noise amplifiers and mixers that have a relatively high sensitivity to noise and interference. The RF circuitry in some applications, such as in mobile communication cellular handsets, may be required to detect signals as small as a few micro-volts or less in amplitude. It is thus often critical to minimize noise and interference from sources external or even internal to the communication apparatus.
In addition to the RF front-end circuitry, typical wireless communication apparatus may also include digital processing circuitry that performs various digital functions including, for example, low level baseband signal processing, implementation of the communication protocol stack, and various user interface functionality. The digital processing circuitry may include a variety of specific hardware such as a DSP (digital signal processor), an MCU (microcontroller unit), hardware accelerators, memory, and/or I/O interfaces, among numerous other specific hardware devices.
Unfortunately, the digital processing circuitry of a typical communication apparatus can be a significant source of detrimental noise and interference. More particularly, the digital processing circuitry in a typical high performance communication apparatus produces digitals signals with relatively small rise and fall times, or with fast transitions or sharp edges. Furthermore, those signals often have relatively high frequencies. As a result, their Fourier series or transforms have rich harmonic contents. The harmonics, or higher-frequency Fourier series components, cause spurious emissions that may interfere with, and may adversely impact, the performance of the RF front-end circuitry. Thus, in many systems, the RF front-end circuitry is implemented on an integrated circuit die that is separate from the integrated circuit die on which the digital processing circuitry is implemented. Additionally, the RF front-end circuitry and digital processing circuitry are often placed in separate electrical cavities, where the shielding of the cavities helps to isolate the electrical and magnetic coupling.
Implementing the RF front-end circuitry and the digital processing circuitry on separate dies, however, has several disadvantages, such as increased component count, size, and overall cost, and more potential for decreased reliability and increased manufacturing failures. It is thus desirable to allow integration of the RF front-end circuitry and digital processing circuitry on a single integrated circuit die without significant degradation and performance due to interference.